1. Field of the Invention
The present invention relates to a system for by-pass control during pipeline operation of a computer.
2. Description of the Related Arts
During a pipeline operation of a computer, a register conflict can occur when a register, in which a change of data is taking place due to execution of a preceding instruction, is referred to by a present instruction. When such a register conflict occurs, reference to this register by the present instruction can be carried out only after completion of the execution of the preceding instruction for a change of data.
Usually the flow of instructions in the pipeline operation consists of a decoding stage D for decoding an instruction, a calculate address stage A for calculating an operand address, a transform address stage T for transforming the operand address into an actual address, a read from buffer stage B for reading the operand from a buffer memory controlled by a storage control circuit, an execute stage E for executing the calculation, and a write result stage W for checking the result of the calculation and writing (storing) the result.